Although technically referring to a semiconductor device having a metal gate electrode and an oxide gate insulator, the term “MOS transistor” is now commonly utilized (and is utilized herein) to refer to any semiconductor device including a conductive gate electrode (whether metal or other conductive material) positioned over a gate insulator (whether oxide or other insulator), which is, in turn, positioned over a semiconductor substrate. The gain of a MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility (μ) of the majority carrier in the transistor channel. The current carrying capacity, and hence the performance of a MOS transistor, is proportional to the mobility of the majority carrier in the channel. The mobility of holes, the majority carrier in a P-channel MOS (PMOS) transistor, can be enhanced by embedding a compressive strain material, such as silicon germanium (SiGe), in the source/drain (S/D) regions of the semiconductor substrate adjacent the opposing channel ends. Conversely, the mobility of electrons, the majority carrier in an N-channel MOS (NMOS) transistor, can be increased by embedding a tensile strain material, such as carbon-doped silicon (SiC), in the S/D regions and adjacent the channel ends. Conventionally-known stress engineering methods are capable of greatly enhancing transistor performance by improving drive current and switching speed without increasing device size and capacitance.
Embedding of strain material within a transistor's S/D regions is often accomplished by first etching cavities in the S/D regions and epitaxially growing a chosen strain material within the cavities. In certain cases, the epitaxial growth process may be continued well-beyond the point at which the cavities are filled with strain material to form a column of strain material projecting upward from the substrate's upper surface (referred to herein as the “strain material overgrowth region”). In the case of epitaxially-grown SiGe embedded within the S/D regions of a PMOS transistor, it may be desirable to produce such a strain material overgrowth region for several reasons, including: (i) to impart greater stress to the PMOS channel region by increasing the overall volume of the epitaxially-grown SiGe; (ii) to provide excess strain material to be consumed during slicidation; and/or (iii) to offset tensile stress applied to the PMOS channel region by a tensile stress liner, which may be blanket deposited over both the PMOS and NMOS transistors to enhance the performance of the NMOS transistors.
While providing the above-described benefits, the formation of strain material overgrowth regions (or other electrically-conductive raised structures) adjacent the transistor gates results in at least one significant disadvantage. Due to the relatively narrow lateral gap separating each strain material overgrowth region and the sidewall of the neighboring gate, which is filled with a dielectric material during the circuit fabrication process, relatively high parasitic fringing capacitances are typically created between the gate and the neighboring overgrowth regions. As the transistors switch states, each of these parasitic fringing capacitances requires charging and discharging. Thus, when considered collectively, the parasitic fringing capacities can greatly reduce the overall operational speed and performance of the completed integrated circuit.
Considering the above, it is desirable to provide embodiments of an integrated circuit fabrication process wherein strain material overgrowth regions are formed over the transistor source/drain regions to provide the above-noted benefits, while parasitic fringing capacitances are reduced in the finished circuit to enhance performance. More generally, it is desirable to provide embodiments of an integrated circuit fabrication process wherein parasitic fringing capacitances between the transistor gates and neighboring raised electrically-conductive structures, such as strain material overgrowth regions or raised source/drain regions, are significantly reduced. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Technical Field and Background.